公司名称

亚创(上海)工程技术有限公司

项目名称

FPGA

需求描述

The role

In this role, you will have the opportunity to work with Telecom Industry Leaders in order to improve their capacity to deliver high value services to their customers. In this context, you will:

· Transceiver: familiar with Xilinx GTH/GTY transceiver structure.

· Joined at least one project to use Xilinx transceiver. Familiar with Xilinx transceiver debug method, such loopback, prbs check is preferred.

· Protocol: Familiar with I2C, SPI, AXI bus. Familiar with CPRI and JESD204B protocol is preferred.

· Block design: Can use Xilinx tool to design Block design is preferred.

Profile

In order to fulfil the role, we are looking for talented candidates with the following profile:

Major in Electronics Engineering, Communication Engineering

1~2 year experience of high-speed design, eg.. transceiver, CRPI, ETH, Rapid IO…

Have FPGA timing constraints and analyze experience is preferred

Familiar with the architecture of ZYNQ MPSOC or microblaze is preferred;